With its Application Notes, Würth Elektronik deals in detail with challenging issues regarding the design of circuits, providing valuable tips for practical applications. This new Application Note, ANP098 “Effect of layout, vias, and design on the blocking quality of filter capacitors” is aimed at blocking capacitors, which filter out higher frequencies from the signal path by deriving RF signals superimposing a DC against the ground.
Using real measurements and practically realistic simulations, PCB-layout techniques for filter and blocking capacitors are also described which are ideally suited for the supply pins of digital ICs.
Filter capacitors
Nadler describes the effects of layout, vias, and design on the blocking quality of filter capacitors
This Application Note was written by Field Application Engineer Andreas Nadler, whose job at Würth Elektronik eiSos is located in the Business Unit for passive and active components and who is responsible for the EMC-conform design of power-supply systems and the suppression screening of electronic modules.
In his AppNote, Nadler describes the effects of layout, vias, and design on the blocking quality of filter capacitors, a topic that is otherwise dealt with in handbooks only at the theoretical level.
Reduced magnetic field
The fundamental task of blocking capacitors on supply pins is basically to short-circuit the clocked current loop of the digital circuits locally using a low impedance. This reduces the radiated magnetic field strength and the RF interference currents coupled into the supply voltage level as much as possible.
If the capacitors are optimally selected about their impedance curve and geometrically optimally placed at the VCC pins, then the clocked RF current can be blocked in the best possible way.
Avoiding mistakes
The new AppNote ANP098 aims to illustrate the influence that the MLCC design, the number of ground vias, and the placement of the filter components have on each other.
In addition, it is clearly shown how unexpected problems can arise as a result of the unfortunate dimensioning of capacitor banks.
